I'd be interested in trying this, at least. I don't know anything about formal verification in the context of FPGAs though.
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Replying to @SamuelAFalvoII
You should definitely look into it.
@oe1cxw is convinced its a VERY powerful tool to find bugs in circuitry (like CPUs ;-)1 reply 0 retweets 0 likes -
Where do I sign up? :)
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You're looking for feedback with the formal verification features of Yosys and said I could help. I'm willing to try, >>
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>> but I am completely new to the practice (but not to the concept).
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Just wondering what I need to do/get/etc to get started.
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Replying to @SamuelAFalvoII
my guess is
@oe1cxw is willing you give you some handholding once you are done withhttps://media.ccc.de/v/33c3-7922-formal_verification_of_verilog_hdl_with_yosys-smtbmc …1 reply 0 retweets 1 like -
Finally watched; NICE! This is design-by-contract applied to hardware, with the additional benefit of automated testing. +1
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I wish I had this for my day-to-day software development tasks too.
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for C/C++ you can use ESBMC or CBMC. There are also tools for other languages.
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