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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Dec 2016
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      Literally the first design I run through @XilinxInc Vivado 2016.4 segfaults in "opt_design -sweep -propconst -resynth_seq_area".pic.twitter.com/8cp3GEVpEd

      2 replies 4 retweets 11 likes
    2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Dec 2016
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      Replying to @oe1cxw

      I have filed SR# 10380604, asking them to file a CR for this bug. It is going to be my 6th Xilinx CR for a bug this year.

      2 replies 0 retweets 1 like
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Dec 2016
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      Replying to @oe1cxw

      At least with a segfault it should be easy to convince Xilinx support that it is a bug in Vivado. Getting them to create a CR can be hard..

      1 reply 0 retweets 2 likes
    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Dec 2016
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      Replying to @oe1cxw

      If anyone wants to reproduce the bug, here is the example design that triggers it: http://svn.clifford.at/handicraft/2016/vivadosig11/ …

      1 reply 1 retweet 1 like
    5. Sachin Bhutada‏ @sachin_bhutada 21 Dec 2016
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      Replying to @oe1cxw

      what if u dont give any switches to opt_design?

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Dec 2016
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      Replying to @sachin_bhutada

      As the log I posted suggests, the problem is -resynth_seq_area, but just -resynth_area is sufficient to crash Vivado.

      3:52 AM - 21 Dec 2016
      1 reply 0 retweets 0 likes
        1. Sachin Bhutada‏ @sachin_bhutada 21 Dec 2016
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          Replying to @oe1cxw

          i see that..just curious to know what happens with opt_design without any switches

          0 replies 0 retweets 0 likes
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