Literally the first design I run through @XilinxInc Vivado 2016.4 segfaults in "opt_design -sweep -propconst -resynth_seq_area".pic.twitter.com/8cp3GEVpEd
-
I have filed SR# 10380604, asking them to file a CR for this bug. It is going to be my 6th Xilinx CR for a bug this year.
At least with a segfault it should be easy to convince Xilinx support that it is a bug in Vivado. Getting them to create a CR can be hard..
-
-
If anyone wants to reproduce the bug, here is the example design that triggers it: http://svn.clifford.at/handicraft/2016/vivadosig11/ …
-
what if u dont give any switches to opt_design?
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.