Literally the first design I run through @XilinxInc Vivado 2016.4 segfaults in "opt_design -sweep -propconst -resynth_seq_area".pic.twitter.com/8cp3GEVpEd
I have filed SR# 10380604, asking them to file a CR for this bug. It is going to be my 6th Xilinx CR for a bug this year.
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Was ISE this poorly behaved when you still used it?
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Everything about ISE is horrible compared to Vivado. (ISE supports XDL and Vivado doesn't. But other than that ISE is just horrible)
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At least with a segfault it should be easy to convince Xilinx support that it is a bug in Vivado. Getting them to create a CR can be hard..
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If anyone wants to reproduce the bug, here is the example design that triggers it: http://svn.clifford.at/handicraft/2016/vivadosig11/ …
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