Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

Many problems on the official @risc_v mailing lists. How do interrupts work? Why can't I build gcc? Etc. >>

THIS is why I choose to simplify to the extreme. Custom build tools that I know work reliably. IRQ management in peripherals, not some >>

>> complicated PLIC device. Non-ELF loader formats. Simple OS APIs, with simple ABIs. A real opportunity to start fresh, but >>

>> all I see is "Linux does it this way, so must be the right way." Critical thought exists, but is directed to solving the wrong problems.

#Kestrel3 might be just a "toy". But at least it's a toy I'll be proud of. And, I hope others will enjoy using/coding for it as well.

I hope that @oe1cxw will hammer hard with his risc-v formal verification tools on kestrel to give you good feedback.

Are you planning on adding a risc-v formal interface (rvfi) to your Polaris CPU? @ico_TC https://github.com/cliffordwolf/riscv-formal/blob/master/README.md#risc-v-formal-interface-rvfi …

I wasn't planning on it. This is the first I've heard of such a thing.