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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Vertigo‏ @SamuelAFalvoII 10 Dec 2016
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      Many problems on the official @risc_v mailing lists. How do interrupts work? Why can't I build gcc? Etc. >>

      1 reply 1 retweet 1 like
    2. Vertigo‏ @SamuelAFalvoII 10 Dec 2016
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      Replying to @SamuelAFalvoII

      THIS is why I choose to simplify to the extreme. Custom build tools that I know work reliably. IRQ management in peripherals, not some >>

      1 reply 0 retweets 0 likes
    3. Vertigo‏ @SamuelAFalvoII 10 Dec 2016
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      Replying to @SamuelAFalvoII

      >> complicated PLIC device. Non-ELF loader formats. Simple OS APIs, with simple ABIs. A real opportunity to start fresh, but >>

      1 reply 0 retweets 0 likes
    4. Vertigo‏ @SamuelAFalvoII 10 Dec 2016
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      Replying to @SamuelAFalvoII

      >> all I see is "Linux does it this way, so must be the right way." Critical thought exists, but is directed to solving the wrong problems.

      1 reply 2 retweets 7 likes
    5. Vertigo‏ @SamuelAFalvoII 10 Dec 2016
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      Replying to @SamuelAFalvoII

      #Kestrel3 might be just a "toy". But at least it's a toy I'll be proud of. And, I hope others will enjoy using/coding for it as well.

      1 reply 1 retweet 4 likes
    6. OSS FPGA & ASIC EDA tools‏ @ico_TC 11 Dec 2016
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      Replying to @SamuelAFalvoII

      I hope that @oe1cxw will hammer hard with his risc-v formal verification tools on kestrel to give you good feedback.

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 11 Dec 2016
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      Replying to @ico_TC @SamuelAFalvoII

      Are you planning on adding a risc-v formal interface (rvfi) to your Polaris CPU? @ico_TC https://github.com/cliffordwolf/riscv-formal/blob/master/README.md#risc-v-formal-interface-rvfi …

      12:37 AM - 11 Dec 2016
      • 1 Retweet
      • Dimitar Tomov
      1 reply 1 retweet 0 likes
        1. New conversation
        1. Vertigo‏ @SamuelAFalvoII 11 Dec 2016
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          Replying to @oe1cxw @ico_TC @github

          I wasn't planning on it. This is the first I've heard of such a thing.

          3 replies 0 retweets 1 like
        2. Vertigo‏ @SamuelAFalvoII 11 Dec 2016
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          Replying to @SamuelAFalvoII @oe1cxw @ico_TC

          Looks easy enough to support overall, and I already support the trap proposal (trap_o and cause_o are exposed).

          2 replies 0 retweets 1 like
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