@scanlime BLIF to schematic (for small circuits):
yosys -p 'read_verilog -lib +/ice40/cells_sim.v;; show' example.blif
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@scanlime BLIF to schematic (for small circuits):
yosys -p 'read_verilog -lib +/ice40/cells_sim.v;; show' example.blif
