@alastair_d_reid Jfyi: I've now started to work on riscv-formal, an ISA verification framework for RISC-V cores:https://github.com/cliffordwolf/riscv-formal …
-
.
@alastair_d_reid First bug: cond branch does not trap on jump to non-word-aligned addr on PicoRV32 core without compressed ISA support.
I think it's the same for unconditional branch, but I have not added the model for that insn yet..
-
-
Nice! We went through a period of happiness catching bugs other test methods could have easily caught but were not yet able to.
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
And then an even happier phase catching bugs that we didn’t think other techniques would have caught. Enjoy!
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.