very very cool
@alastair_d_reid Jfyi: I've now started to work on riscv-formal, an ISA verification framework for RISC-V cores:https://github.com/cliffordwolf/riscv-formal …
-
-
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
Cool, tweet when you find your first bug with it! Really curious to see whether your experience is like ours.
-
.
@alastair_d_reid First bug: cond branch does not trap on jump to non-word-aligned addr on PicoRV32 core without compressed ISA support. - Show replies
New conversation -
-
-
coolest thing I heard in a while. If you need help I am willing to contribute
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.