Anybody know if *optimal* (not real/practical) FPGA/ASIC routing is NP-hard or harder than that?
btw, "NP-hard" already means "NP-complete or harder". So there is no harder than NP-hard. :)
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Ah, true. What I meant to say was, I do not believe a polynomial-time algorithm for checking optimality of an FPGA placement exists
Thanks. Twitter will use this to make your timeline better. UndoUndo
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