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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      RTLIL.SigSpec(false/true)?

      1 reply 0 retweets 0 likes
    2. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      That's not helping -- opt_clean is somehow detecting the SRLs as "unused" bocks

      1 reply 0 retweets 0 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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      Replying to @nachiketkapre

      are the SRL outputs connected to a cone that contributes to a module primary output?

      2 replies 0 retweets 0 likes
    4. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @oe1cxw

      I was relying on "first_cell->setPort(q_port, last_cell->getPort(q_port));" in process_chain() to wire SRL outputs for me

      2 replies 0 retweets 0 likes
    5. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      fixup() for GreenPak4 only wires the inputs and some taps

      1 reply 0 retweets 0 likes
    6. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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      Replying to @nachiketkapre

      fixup() for GP4 connects outputs (OUT[AB], OUT[AB]_TAP). Your code seems to leave Q unconnected.

      2 replies 0 retweets 0 likes
    7. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @oe1cxw

      BINGO! Wired Q port to Q, and rename IN port on GreenPak to D input of SRL16. Now see the SRL16s in the output...

      1 reply 0 retweets 0 likes
    8. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      Still need to translate the DEPTH into A0-A3 constants, and extend support for SRL32s

      1 reply 0 retweets 0 likes
    9. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      Check my commit if its sensible/correct -- https://github.com/nachiket/yosys/commit/4c80ad58337aeee27c3048c9a845c4ea570febbb …

      1 reply 0 retweets 1 like
    10. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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      Replying to @nachiketkapre

      looks good. you shouldn't need the "depth" argument: this should be equal to the one entry in "taps".

      2 replies 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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      Replying to @oe1cxw @nachiketkapre

      Xilinx SRLs only have one tap. Your analyze() functions should reflect that.

      8:02 AM - 23 Nov 2016
      1 reply 0 retweets 0 likes
        1. New conversation
        1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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          Replying to @oe1cxw @nachiketkapre

          something like: if (GetSize(taps) > 1) return false; if (taps.at(0) > 16) return false;

          1 reply 0 retweets 1 like
        2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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          Replying to @oe1cxw @nachiketkapre

          SRL16E that is. SRLC32E have a Q that depends on A and also a Q31.

          1 reply 0 retweets 1 like
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