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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @oe1cxw

      Where would I invoke shregmap in the synth_xilinx sequence? Under the "fine:" set of optimization passes?

      1 reply 0 retweets 0 likes
    2. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      I put it under dff2dffe, but get no conversions...

      1 reply 0 retweets 0 likes
    3. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      Some progress, (1) Put shregmap before cell_map.v pass, (2) clkpol and enpol set to "pos"

      1 reply 0 retweets 0 likes
    4. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      I see "Converting .. to a shift register" messages, but later on get an error "GP_SHREG" not part of design during Analyze Hierarchy

      1 reply 0 retweets 0 likes
    5. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      Ahh GP_SHREG is only a GreenPak4 primitive.. Need to find the Xilinx version

      1 reply 0 retweets 1 like
    6. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      Almost there -- the SRLs are getting thrown out later -- think I need to configure A0-A3 inputs with constants..

      1 reply 0 retweets 0 likes
    7. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      Not sure what's the mechanism to initialize ports with 0 or 1 constants...

      1 reply 0 retweets 0 likes
    8. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      RTLIL.SigSpec(false/true)?

      1 reply 0 retweets 0 likes
    9. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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      Replying to @nachiketkapre @oe1cxw

      That's not helping -- opt_clean is somehow detecting the SRLs as "unused" bocks

      1 reply 0 retweets 0 likes
    10. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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      Replying to @nachiketkapre

      are the SRL outputs connected to a cone that contributes to a module primary output?

      2 replies 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 23 Nov 2016
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      Replying to @oe1cxw @nachiketkapre

      I'll have a look at your code if you provide me with a diff with your changes (or a git link I can clone).

      7:27 AM - 23 Nov 2016
      1 reply 0 retweets 0 likes
        1. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 23 Nov 2016
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          Replying to @oe1cxw

          https://github.com/nachiket/yosys/commit/fa8118fe37ff7215b1ea6841b8cb3ec82c2cd937 …

          0 replies 0 retweets 0 likes
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