You'd probably need to add a simple ShregmapTechXilinx class.
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That's not helping -- opt_clean is somehow detecting the SRLs as "unused" bocks
are the SRL outputs connected to a cone that contributes to a module primary output?
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I'll have a look at your code if you provide me with a diff with your changes (or a git link I can clone).
New conversation -
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I was relying on "first_cell->setPort(q_port, last_cell->getPort(q_port));" in process_chain() to wire SRL outputs for me
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fixup() for GreenPak4 only wires the inputs and some taps
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