@oe1cxw Can I run shregmap in conjunction with synth_xilinx? Will it extract Xilinx SRLs?
shregmap should be integrated into the synth_xilinx flow to extract SRLs. This has not been done yet. Shouldn't be hard tho.
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Open a github issue for that to increase the social pressure on me to do that. :) Right now it's not a priority..
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Is this a simple matter or adding shregmap to the synth_xilinx recipe? or does the https://github.com/cliffordwolf/yosys/blob/master/passes/techmap/shregmap.cc … file need to change?
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