@oe1cxw This came up in a Xilinx paper I've been reading today: How difficult would it be to add between-clock-domain timing >>
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analysis to icetime, when the phase relationship/delay between the clocks is known? E.g. Using two PLLs to phase align clk and 2*clk
the plan is to use opentimer for more advanced timing analysis. But this still needs some work.
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I have a design where it would be helpful (but not required) to treat two phase-aligned clks (integer multiples) as synchronous. >>
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Naturally, b/c I've no clue how I'd write timing analysis s/w for this case, my first question is: "How would I write s/w for this?"
End of conversation
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