Just finished my latest blog post on IP-XACT http://olofkindgren.blogspot.com/2016/11/ip-xact-good-bad-and-outright-madness.html …
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Well, that's a bug in the IP-XACT file then, and you will see it in the generated verilog
Usually you don't manually check generated verilog, not on that level. You'd see that the generated system doesn't work.
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And how would you fix it: You can only use the vendor A definition and break the vendor B core or vice versa.
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You'd have to manually change the cores of one vendor to use a different bus VNLV and create an interface abstractor to fix.
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