@oe1cxw Is your policy with Yosys to *not* add additional error checking in read_verilog (i.e. patches to add checks will be rejected)?
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Good to know. I'm working on requirements for a Verilog linter (https://github.com/azonenberg/openfpga/wiki/Linter-notes …)
maybe "verilator --lint-only" would be a better basis for that than Yosys' read_verilog.
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At this point I'm trying to build a list of RTL footguns, then figure out the best tool, existing or not, to use for the check later
Thanks. Twitter will use this to make your timeline better. UndoUndo
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