@oe1cxw Is your policy with Yosys to *not* add additional error checking in read_verilog (i.e. patches to add checks will be rejected)?
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Or is it simply not a priority for your own development efforts
It's not a priority. But I'll accept patches as long as they are reasonably simple. (And small. Small is always good.. :)
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Good to know. I'm working on requirements for a Verilog linter (https://github.com/azonenberg/openfpga/wiki/Linter-notes …)
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Some items best done by an external tool, but some will be easier to implement as yosys passes on post-synth netlists
End of conversation
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