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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 17 Oct 2016
    • Report Tweet
    • Report NetzDG Violation

    More multiclock formal verification stuff. Yosys-SMTBMC can now prove the property in this example:pic.twitter.com/rG2CCUCbVL

    4:45 AM - 17 Oct 2016
    • 1 Retweet
    • 10 Likes
    • scam Oleg Nenashev Carlos Parra Drew Fustini 🐧 #BlackLivesMatter Juan Antonio Rufes Matt vincent zimmer Juan Gonzalez whitequark
    1 reply 1 retweet 10 likes
      1. OSS FPGA & ASIC EDA tools‏ @ico_TC 17 Oct 2016
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        Replying to @oe1cxw

        "You also probably need a clock domain crossing checker. Cost you maybe another used car price."http://hackaday.com/2016/10/10/the-journey-toward-a-completely-open-microcontroller/#comment-3227142 …

        0 replies 0 retweets 1 like
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