But don't hold your breath! I estimate it's >1 year until this can be used for anything interesting..
Buckle up! Another storm is brewing. I've now started doing serious work on documenting the Xilinx 7-series bit-stream format.pic.twitter.com/uGvF9x3p2p
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whoa, what gives? I thought you were too burned out on bitstream RE
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Somebody has to do it, and it doesn't seem like anyone else is going to do it anytime soon.. :)
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Also: I'm going to take my time this time and focus on also documenting my process.
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Hopefully this will make it easier to find collaborators so I don't need to do all the work myself.
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Is there anything we can do to help? Don't really have time, but do have hardware and could possible donate money.
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Will surely post a "request for contributors" at some time in the future. I would love to make this project a community effort. 1/
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But first I have to get the basics done, maybe a few months.. I do take donations on the Yosys website, btw: http://www.clifford.at/yosys/donate.html …
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I'll probably be using VPR for Xilinx place and route. I estimate >1 year until it will be useful for anything.
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@elaforest@azonenberg you will like this. -
<3 <3 <3
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Wow Clifford! This is awesome!
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Wow Xilinx 7-series bit stream support would be a massive win
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I run into a paper about this recently and just saw, that the complete thesis is online. google: "Open-Source Bitstream Generation"
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Excellent!
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hey
@XilinxInc how about you just give up and release the specs now?@oe1cxwThanks. Twitter will use this to make your timeline better. UndoUndo
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