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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 22 Sep 2016
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    Does anyone have experience with porting VPR (i.e. writing VPR device descriptions)? #askingforafriend

    2:50 AM - 22 Sep 2016
    • 2 Retweets
    • 1 Like
    • Dimitar Tomov OSS FPGA & ASIC EDA tools
    1 reply 2 retweets 1 like
      1. New conversation
      1. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 22 Sep 2016
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        Replying to @oe1cxw

        I muddled briefly with VPR's crazy XML syntax for architecture descriptions.. I couldn't trivially figure out a way to port Lattice

        1 reply 0 retweets 1 like
      2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 22 Sep 2016
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        Replying to @nachiketkapre

        actually, my friend might be interested in using it for xilinx 7-series place and route..

        1 reply 0 retweets 1 like
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