Also: v2c uses a non-open source Verilog front-end. Yosys C back-end is back on the todo list..https://twitter.com/oe1cxw/status/768433225387634688 …
I was more thinking about ESBMC (since I know that one already), but yes, that is the idea. E.g. checking CPUs against C specs.
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"CPUs against C specs"? HW cpu verilog to C-model checked with software verifier or something else?
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for example. You could do all sorts of things with a C model that is optimized for model checking.
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