Is there any free or free-as-in-free-beer Verilog sim that supports SVA properties? I need a reference implementation to check against..
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Hace you looked at Verilator http://www.veripool.org/wiki/verilator
checked again with current git head. verilator doesn't seem to support what I need. Code example: http://www.edaplayground.com/x/2Z2E
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Sorry that was my best shot..
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is the problem that verilator does not handle the ##1 delay?
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No. It already fails at the "property" keyword. (Jfyi: ##1 is not a "delay" in the sense that #1 is. It's clocked.)
End of conversation
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