I think I’ll be able to write an FPGA synthesiser after I’m done with this CPU prototype project…
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@ico_TC@MayaPosch What about dumb people? Cause I've looked through the yosys source and it's complicated... -
opinions about objective topics, such as technical and engineering topics, should be argumented ;) cc
@oe1cxw@ico_TC@MayaPosch
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