If anyone is giving those out, I'd like one also. I'd even settle for the second- or third-largest.
-
-
Replying to @brouhaha @whitequark
In exchange for reversing it? Any day! Just tell me.
2 replies 0 retweets 1 like -
Replying to @ico_TC @whitequark
I'm willing to devote some time and effort to reverse-engineering FPGAs, but certainly wouldn't start with the biggest.
5 replies 1 retweet 4 likes -
I think reverse-engineering even the smallest Spartan 6 or Artix 7 FPGAs would be very worthwhile.
2 replies 0 retweets 1 like -
Spartan 6 is a dead end by this point. anything from series 7 is sensible though
3 replies 0 retweets 1 like -
(well, a good chunk of S6 is reversed by Wolfgang Spraul already, even with some very hacky code)
1 reply 0 retweets 1 like -
Replying to @whitequark @ico_TC
Has Wolfgang Spraul published his S6 reverse-engineering results? Presumably 7-series is not completely dissimilar.
4 replies 0 retweets 0 likes -
Would certainly be interested in reading about his methods, if nothing else.
1 reply 0 retweets 0 likes -
Replying to @brouhaha
Step one of his method: Read >all< documentation about the chip from Xilinx carefully!!! Step 2: Learn Tcl
1 reply 1 retweet 1 like -
Replying to @ico_TC
Not sure why I'd need to learn Tcl. Can generate Xilinx NCD file from any language, e.g., Python, C++, etc.
2 replies 0 retweets 0 likes
NCD is deprecated. Doesn't work with Vivado (and thus newer chips). (Same for XDL of course.)
-
-
That's aggravating. In that case, I'd probably use ISE 14.7, which had support for most 7-series devices.
0 replies 0 retweets 0 likesThanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.