Verilog gurus, there has to be a simpler, better way than https://github.com/sam-falvo/polaris/blob/master/rtl/verilog/decode.v … . Can anyone advise?
Maybe using one large "casez ({ir_i, trap_i, defined_i})" instead of case cascade would help?
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Looks like iverilog does not support casez statements. I get a syntax error. :(
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I'm certain it does support casez statements.
End of conversation
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