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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 3 Aug 2016
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      A little preview of Chipy, a Python API for creating Verilog code generators. (PM me for the link to the svn repo.)pic.twitter.com/0mgf8ra61o

      3 replies 12 retweets 20 likes
    2. Olof Kindgren‏ @OlofKindgren 3 Aug 2016
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      Replying to @oe1cxw

      Would be interesting to hear why you did this instead of going with migen or MyHDL

      2 replies 0 retweets 4 likes
    3. Eric LaForest‏ @elaforest 3 Aug 2016
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      Replying to @OlofKindgren @oe1cxw

      Indeed! And does it generate Verilog-2001? (I hope so!)

      1 reply 0 retweets 2 likes
    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 3 Aug 2016
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      Replying to @elaforest @OlofKindgren

      @cr1901 Re MyHDL: It doesn't even preserve design hierarchy. Also: Too high-level. It is almost a Py HLS tool. 1/

      1 reply 0 retweets 0 likes
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 3 Aug 2016
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      Replying to @oe1cxw @elaforest and

      Re Migen: The way the Migen If, Else, .. etc objects work make it hard to interleave with other code. 2/

      2 replies 0 retweets 0 likes
    6. William D. Jones‏ @cr1901 3 Aug 2016
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      Replying to @oe1cxw @elaforest @OlofKindgren

      I'm not sure I follow :(... you can always add If, Else, etc after the fact by: self.my_submodule.sync +=

      1 reply 0 retweets 0 likes
    7. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 3 Aug 2016
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      Replying to @cr1901 @elaforest @OlofKindgren

      I have not said it's impossible, only that I find it hard to use.

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 3 Aug 2016
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      Replying to @oe1cxw @cr1901 and

      I'm not claiming that everyone will share my opinion on this matter. Use whatever you prefer..

      9:39 AM - 3 Aug 2016
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      3 replies 0 retweets 1 like
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        1. William D. Jones‏ @cr1901 3 Aug 2016
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          Replying to @oe1cxw

          FWIW, My main reasons for using Migen are: "structs of wires by purpose", "generate sucks", and "build file generation".

          1 reply 0 retweets 0 likes
        2. William D. Jones‏ @cr1901 3 Aug 2016
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          Replying to @cr1901 @oe1cxw

          Emphasis on the second one: HOLY hell, Verilog generate sucks.

          1 reply 0 retweets 0 likes
        3. Show replies
        1. William D. Jones‏ @cr1901 3 Aug 2016
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          Replying to @oe1cxw

          (I wanted you to clarify what you meant by "interleaving code"; I think I misunderstand. Not preaching the Church of Migen today!)

          0 replies 0 retweets 0 likes
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        1. Olof Kindgren‏ @OlofKindgren 3 Aug 2016
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          Replying to @oe1cxw @cr1901 @elaforest

          Not trying to start a flame war. Just curious since I know you're aware of the others and probably had a reason

          0 replies 0 retweets 1 like
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