A little preview of Chipy, a Python API for creating Verilog code generators. (PM me for the link to the svn repo.)pic.twitter.com/0mgf8ra61o
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@cr1901 Re MyHDL: It doesn't even preserve design hierarchy. Also: Too high-level. It is almost a Py HLS tool. 1/
Re Migen: The way the Migen If, Else, .. etc objects work make it hard to interleave with other code. 2/
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I might have to say more about Chipy vs. Migen vs. MyHDL when Chipy is release-ready. /3
Thanks. Twitter will use this to make your timeline better. UndoUndo
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I'm not sure I follow :(... you can always add If, Else, etc after the fact by: self.my_submodule.sync +=
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I have not said it's impossible, only that I find it hard to use.
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