Wrote a post about limitations of the ISA-Formal technique for verifying processors #CAV2016 #ARM
https://alastairreid.github.io/alastairreid.github.io/isa-formal-limitations/ …
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The big problem with SV is that there is no standard that defines a synthesizable subset (other than with Verilog). 1/
So every vendor has to make its own definition where to draw the line between synthesizable and non-synthesizable. 2/
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And formal is an entirely new 3rd category of something that must be some subset of full SV, but isn't well defined.. 3/
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Are you using SV only in your checker code, or is the design SV as well? Any chance you guys will release code examples? /4
End of conversation
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