Wrote a post about limitations of the ISA-Formal technique for verifying processors #CAV2016 #ARM
https://alastairreid.github.io/alastairreid.github.io/isa-formal-limitations/ …
The issues with tools having bad Verilog language support you mentioned in the blog post: Verilog or SystemVerilog / SVA?
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Worst with SV. Made worse by me machine generating code so my code was already a bit unusual.
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The big problem with SV is that there is no standard that defines a synthesizable subset (other than with Verilog). 1/
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