#verilog limitation that bugs me most: cannot use a parameter as a literal width. e.g.: WORD_WIDTH'd42 is illegal, and complicates code.
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My solution is often along the lines of: integer one = 1; ... foo + one[WORD_WIDTH-1:0]; to avoid width mismatch warnings.
This may yield undef bits for WORD_WIDTH > 32. (_may_ because size of integer is implementation defined.)
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Very true. I had since switched to using the form localparam zero = {WORD_WIDTH{1'b0}}; which doesn't have that prob.
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