Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

In the top-level, I initialize it to 1 on reset. When a certain condition is met, I want it to be reset to zero and NEVER be set >>

back to 1 unless another power-on reset occurs. I accidentally wrote the condition such that it was always true. yosys decided to >>

replace the net with the constant 0. Is ignoring the initial value in this case a bug?

https://dl.dropboxusercontent.com/u/20852311/delay_line.zip … main_delay_fifo is the signal in question that gets optimized out. See top.rpt.

Ignore what I said about "constant driver 0". That was a mistake. I still think it shouldn't be optimized out tho.

why? it seems to be a perfectly legal optimization..

B/c the initial value is 1. Sematically, it should change to 0 at the first posedge of the system clock? Is the state of a >>