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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @cr1901

      .. but you said it was set to the wrong const value, correct? that sounds like it could be a bug.

      1 reply 0 retweets 0 likes
    2. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @oe1cxw

      In the top-level, I initialize it to 1 on reset. When a certain condition is met, I want it to be reset to zero and NEVER be set >>

      1 reply 0 retweets 0 likes
    3. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @cr1901 @oe1cxw

      back to 1 unless another power-on reset occurs. I accidentally wrote the condition such that it was always true. yosys decided to >>

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    4. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @cr1901 @oe1cxw

      replace the net with the constant 0. Is ignoring the initial value in this case a bug?

      1 reply 0 retweets 0 likes
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @cr1901

      It shouldn't ignore the initial value. The results I get for the following example look fine at least.pic.twitter.com/Rwe4n5ULVj

      2 replies 0 retweets 0 likes
    6. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @oe1cxw

      https://dl.dropboxusercontent.com/u/20852311/delay_line.zip … main_delay_fifo is the signal in question that gets optimized out. See top.rpt.

      1 reply 0 retweets 0 likes
    7. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @cr1901 @oe1cxw

      Ignore what I said about "constant driver 0". That was a mistake. I still think it shouldn't be optimized out tho.

      1 reply 0 retweets 0 likes
    8. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @cr1901

      why? it seems to be a perfectly legal optimization..

      1 reply 0 retweets 0 likes
    9. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @oe1cxw

      B/c the initial value is 1. Sematically, it should change to 0 at the first posedge of the system clock? Is the state of a >>

      2 replies 0 retweets 0 likes
    10. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @cr1901

      Why would it change to 0 on first system clock? It is only assigned 0 in a block that cannot be activated bc its effectively if(0).

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @oe1cxw @cr1901

      Proof that it cannot ever change to 0: yosys -p 'prep; memory_map; sat -seq 1 -prove main_delay_fifo 1' top.v

      5:17 AM - 14 Jul 2016
      2 replies 0 retweets 0 likes
        1. William D. Jones‏ @cr1901 14 Jul 2016
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          Replying to @oe1cxw

          Okay, then I misunderstand how Verilog handles compares of nets of different widths then. So nevermind then :D. Oops...

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        1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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          Replying to @oe1cxw @cr1901

          oops, wrong proof. change "-seq 1" to "-tempinduct" to prove the property for all time, not just initial state.

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