I'm afraid that code's long gone since yesterday... I'll try to dupe within the hour. FWIW, I think yosys's right to remove it. >>
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B/c the initial value is 1. Sematically, it should change to 0 at the first posedge of the system clock? Is the state of a >>
Why would it change to 0 on first system clock? It is only assigned 0 in a block that cannot be activated bc its effectively if(0).
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Proof that it cannot ever change to 0: yosys -p 'prep; memory_map; sat -seq 1 -prove main_delay_fifo 1' top.v
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Okay, then I misunderstand how Verilog handles compares of nets of different widths then. So nevermind then :D. Oops...
End of conversation
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