It gets better; the net was removed b/c its value depended on comparing a 3-bit signal (by mistake) to >= 256, which is always true?
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Ignore what I said about "constant driver 0". That was a mistake. I still think it shouldn't be optimized out tho.
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B/c the initial value is 1. Sematically, it should change to 0 at the first posedge of the system clock? Is the state of a >>
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Verilog design invalid before the first posedge of a system clock?
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