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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. William D. Jones‏ @cr1901 13 Jul 2016
      • Report Tweet
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      Replying to @cr1901 @oe1cxw

      Like "net X was removed b/c it was proven it is always 0."

      1 reply 0 retweets 0 likes
    2. William D. Jones‏ @cr1901 13 Jul 2016
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      Replying to @cr1901 @oe1cxw

      Erm nevermind sorry... it's in the report output. Apologies.

      1 reply 0 retweets 0 likes
    3. William D. Jones‏ @cr1901 13 Jul 2016
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      Replying to @cr1901 @oe1cxw

      I'd like to add- the signal in question initialized to 1 in top level, but yosys replaces it with constant driver 0. XD

      1 reply 0 retweets 0 likes
    4. William D. Jones‏ @cr1901 13 Jul 2016
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      Replying to @cr1901 @oe1cxw

      It gets better; the net was removed b/c its value depended on comparing a 3-bit signal (by mistake) to >= 256, which is always true?

      1 reply 0 retweets 0 likes
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @cr1901

      can you share the code that caused that?

      1 reply 0 retweets 0 likes
    6. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @oe1cxw

      I'm afraid that code's long gone since yesterday... I'll try to dupe within the hour. FWIW, I think yosys's right to remove it. >>

      2 replies 0 retweets 0 likes
    7. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @cr1901

      .. but you said it was set to the wrong const value, correct? that sounds like it could be a bug.

      1 reply 0 retweets 0 likes
    8. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @oe1cxw

      In the top-level, I initialize it to 1 on reset. When a certain condition is met, I want it to be reset to zero and NEVER be set >>

      1 reply 0 retweets 0 likes
    9. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @cr1901 @oe1cxw

      back to 1 unless another power-on reset occurs. I accidentally wrote the condition such that it was always true. yosys decided to >>

      1 reply 0 retweets 0 likes
    10. William D. Jones‏ @cr1901 14 Jul 2016
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      Replying to @cr1901 @oe1cxw

      replace the net with the constant 0. Is ignoring the initial value in this case a bug?

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jul 2016
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      Replying to @cr1901

      It shouldn't ignore the initial value. The results I get for the following example look fine at least.pic.twitter.com/Rwe4n5ULVj

      3:37 AM - 14 Jul 2016
      2 replies 0 retweets 0 likes
        1. William D. Jones‏ @cr1901 14 Jul 2016
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          Replying to @oe1cxw

          Let's see if I can reproduce the behavior/my mistakes...

          0 replies 0 retweets 0 likes
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        1. William D. Jones‏ @cr1901 14 Jul 2016
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          Replying to @oe1cxw

          https://dl.dropboxusercontent.com/u/20852311/delay_line.zip … main_delay_fifo is the signal in question that gets optimized out. See top.rpt.

          1 reply 0 retweets 0 likes
        2. William D. Jones‏ @cr1901 14 Jul 2016
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          Replying to @cr1901 @oe1cxw

          Ignore what I said about "constant driver 0". That was a mistake. I still think it shouldn't be optimized out tho.

          1 reply 0 retweets 0 likes
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