@oe1cxw Is there a yosys switch for "determine what's causing half my design to be optimized away"?
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It gets better; the net was removed b/c its value depended on comparing a 3-bit signal (by mistake) to >= 256, which is always true?
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I'm afraid that code's long gone since yesterday... I'll try to dupe within the hour. FWIW, I think yosys's right to remove it. >>
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Note that the Verilog was autogenerated; I made a careless mistake that caused an intended 8 (actually 10)-bit net to be 3-bits.
End of conversation
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