Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw This might be a stupid q, but in yosys how did you get ahold of SiliconBlue's primitive library (in Verilog form)?

You mean techlibs/ice40/cells_sim.v? I just wrote that myself.

Yes. And is that the file used to infer primitives when my Verilog code is parsed?

(Context: I'm trying to get yosys to infer a pullup on IceStick's GPIO and instantiating an SB_IO seems to be doing nothing :(...)

instantiating the SB_IO (and setting PULLUP=1) should do the trick.

Fixed (kinda... now it's always high)... I forgot to add a clock signal, since inputs are registered by default.

You should always at least specify PIN_TYPE when instantiating SB_IO. Don't rely on defaults.

Are defaults prone to changing (I'm not questioning your judgment. I'm changing it now. Just wondering)? >>