@oe1cxw This might be a stupid q, but in yosys how did you get ahold of SiliconBlue's primitive library (in Verilog form)?
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Yes. And is that the file used to infer primitives when my Verilog code is parsed?
No. It is only used for things like post-synth simulation, and auto-generating blackboxes for manual primitive instantiation.
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See "help synth_ice40" for the whole chain of things that map RTL to primitives.
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It's a mix of custom ice40-specific commands and generic commands such as "techmap" and "abc -lut 4".
End of conversation
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