@oe1cxw This might be a stupid q, but in yosys how did you get ahold of SiliconBlue's primitive library (in Verilog form)?
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Yes. And is that the file used to infer primitives when my Verilog code is parsed?
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(Context: I'm trying to get yosys to infer a pullup on IceStick's GPIO and instantiating an SB_IO seems to be doing nothing :(...)
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