I've just released PonyLink: A single-wire bi-directional chip-to-chip interface for FPGAs on GitHub:https://github.com/cliffordwolf/PonyLink …
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You also scramble the 8b10b encoder output, yes? I seem to recall you had a scrambler in there somewhere.
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Ahh, right. That definitely helps the DC balance. SONET doesn't even encode; it relies only on scrambling.
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If it works for SONET, it should work for PonyLink too. :)
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Scrambling alone can have some downsides - e.g. SDI's pathological signals.
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If your LFSR period exceeds the length of the longest packet, probability of exploitation is near 0.
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So i can see why 8b10b was chosen to ensure that run length was kept to 5 bits or under.
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