I've just released PonyLink: A single-wire bi-directional chip-to-chip interface for FPGAs on GitHub:https://github.com/cliffordwolf/PonyLink …
-
I believe it does: https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt#L164 … But I admit that there is a lot of room for improvement in the wording..
@cr1901 jfyi: I've now improved the "Low-level signaling" section of protocol.txt:https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt#L160 …
-
-
Ahh, I see; it's like you're taking the raw data stream (8b10b encoder output in this case) and >>
-
>> stretching isochronous spans of bits as needed for the asynchronous receiver's benefit. A kind of PWM.
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.