I've just released PonyLink: A single-wire bi-directional chip-to-chip interface for FPGAs on GitHub:https://github.com/cliffordwolf/PonyLink …
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protocol.txt and timing.py say that clk recovery isn't needed, but doesn't explain how it works.
I believe it does: https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt#L164 … But I admit that there is a lot of room for improvement in the wording..
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@cr1901 jfyi: I've now improved the "Low-level signaling" section of protocol.txt:https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt#L160 … -
Ahh, I see; it's like you're taking the raw data stream (8b10b encoder output in this case) and >>
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