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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Jul 2016
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      I've just released PonyLink: A single-wire bi-directional chip-to-chip interface for FPGAs on GitHub:https://github.com/cliffordwolf/PonyLink …

      6 replies 24 retweets 33 likes
    2. William D. Jones‏ @cr1901 5 Jul 2016
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      Replying to @oe1cxw

      "works without a dedicated hardware block for clock recovery"- so an ADPLL you mean :P?

      1 reply 0 retweets 0 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Jul 2016
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      Replying to @cr1901

      no, it's not implementing an adpll. See section on "Low-level signaling" in the protocol spec:https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt …

      1 reply 0 retweets 0 likes
    4. William D. Jones‏ @cr1901 5 Jul 2016
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      Replying to @oe1cxw

      So it's like an advanced UART, sampling in the middle of a pre-defined bit-period, and synchronizing to start of a "frame"?

      2 replies 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Jul 2016
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      Replying to @cr1901

      no. that would require > 2x oversampling. PonyLink usually does better than that. (depending on ratio of master/slave clock rate)

      8:01 AM - 5 Jul 2016
      1 reply 0 retweets 0 likes
        1. William D. Jones‏ @cr1901 5 Jul 2016
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          Replying to @oe1cxw

          Then I don't understand. Seems a bit risky to NOT oversample, but I guess that's what the Python program's for...

          0 replies 0 retweets 0 likes
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