I've just released PonyLink: A single-wire bi-directional chip-to-chip interface for FPGAs on GitHub:https://github.com/cliffordwolf/PonyLink …
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"works without a dedicated hardware block for clock recovery"- so an ADPLL you mean :P?
no, it's not implementing an adpll. See section on "Low-level signaling" in the protocol spec:https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt …
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So it's like an advanced UART, sampling in the middle of a pre-defined bit-period, and synchronizing to start of a "frame"?
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In any case, looks cool! May be a good stress test for IceStick...
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