"works without a dedicated hardware block for clock recovery"- so an ADPLL you mean :P?
I've just released PonyLink: A single-wire bi-directional chip-to-chip interface for FPGAs on GitHub:https://github.com/cliffordwolf/PonyLink …
-
-
-
no, it's not implementing an adpll. See section on "Low-level signaling" in the protocol spec:https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt …
- Show replies
New conversation -
-
-
I'm curious to know more about the physical-layer signaling used. Is there a document which describes it?
-
protocol.txt and timing.py say that clk recovery isn't needed, but doesn't explain how it works.
- Show replies
New conversation -
-
-
Resource cost?
-
On the large side. About 1700 LUTs on iCE40 devices. (This is about the size of a PicoRV32 core.)
- Show replies
New conversation -
-
-
I've done a similar but less fancy and faster (800 Mb/s) core for 7 series: https://github.com/HarmonInstruments/verilog/tree/master/sio … Will consider this for ice40.
-
I used the 7 series ISERDESE2 sampling at an effective 3.2 GS/s. Your encoding may be a nice option for the ICE40.
End of conversation
New conversation -
-
-
Why 8b/10 b, when it doesn't appear to preserve DC balance or run at constant bit rate? Might be scope for better coding scheme...
-
DC balance is preserved well enough to use caps or magnetics in the link. But I haven't done a lot of testing with that.
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.