@oe1cxw https://github.com/cliffordwolf/yosys/issues/182#issuecomment-229590435 … Should've given you the benefit of the doubt that Xilinx was wrong for accepting this code lmao
there is an argument to be had that synth should ignore the bogus io_status initialization. it's hard to say which tool is "right".
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Does Verilog REQUIRE a diagnostic for the error in the generated code? I am wondering why Xilinx accepted it.
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Migen automatically initializes all variables, presumably to guard against bugs. Seems in this case it backfired...
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