Spot the bug! Crap like this is actually part of the IWLS 2005 benchmark code!pic.twitter.com/9A8BIfkBpR
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I probably don't know (remember?) enough about Verilog spec to find the bug...
I don't think so. Just perform the substitution for `DMA_PRI_WIDTH in your head and observe what happens to the -1 in the wire decl.
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Oh... the substitution happens in a phase before evaluation... meaning the -1 gets eaten by the substitution XD.
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My problem was I was trying to evaluate that expression when it first appeared :P.
End of conversation
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