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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jun 2016
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      Spot the bug! Crap like this is actually part of the IWLS 2005 benchmark code!pic.twitter.com/9A8BIfkBpR

      1 reply 5 retweets 4 likes
    2. William D. Jones‏ @cr1901 14 Jun 2016
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      Replying to @oe1cxw

      Why is DMA_PRI_WIDTH not match the number of levels?

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jun 2016
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      Replying to @cr1901

      not the bug

      8:02 AM - 14 Jun 2016
      1 reply 0 retweets 0 likes
        1. New conversation
        1. William D. Jones‏ @cr1901 14 Jun 2016
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          Replying to @oe1cxw

          I probably don't know (remember?) enough about Verilog spec to find the bug...

          1 reply 0 retweets 0 likes
        2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 14 Jun 2016
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          Replying to @cr1901

          I don't think so. Just perform the substitution for `DMA_PRI_WIDTH in your head and observe what happens to the -1 in the wire decl.

          1 reply 0 retweets 0 likes
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