Did you know that Verilog "if" and "case" differs wrt to undefs in synth and sim? Yosys can do it both ways now: https://www.reddit.com/r/yosys/comments/4n4hpo/new_prep_ifx_for_modelling_simulationstyle_if_and/ …
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Did you know that Verilog "if" and "case" differs wrt to undefs in synth and sim? Yosys can do it both ways now: https://www.reddit.com/r/yosys/comments/4n4hpo/new_prep_ifx_for_modelling_simulationstyle_if_and/ …
